1. Field of the Invention
This invention relates to semiconductor packaging technology, and more particularly, to a QFN (Quad Flat Non-leaded) semiconductor package and method of fabricating the same, which is characterized by that it includes a ground-wing structure which is exposed to the bottom outside of the encapsulation body to help enhance the grounding effect and the electrical performance of the packaged chip during operation.
2. Description of Related Art
QFN (Quad Flat Non-leaded) is an advanced semiconductor packaging technology which is characterized by the provision of non-protruding pins (or called leads) on the bottom side of the encapsulation body, which allows the overall package to be made very compact in size. The QFN technology also allows the die pad to be exposed on the bottom side of the encapsulation body. During SMT (Surface Mount Technology) process when the package is mounted on a printed circuit board (PCB), the exposed die pad can be electrically bonded to the PCB""s ground plane, which can help enhance the heat-dissipation efficiency and electrical performance of the packaged chip during operation. For this sake, the QFN technology is particularly useful for the packaging of high-frequency and radio-frequency chips.
One drawback to the conventional QFN technology, however, is that it is unsuitable for the packaging of a semiconductor chip of central-pad type whose I/O pads are located along a center line in the active surface thereof, such as DRAM (Dynamic Random Access Memory) chips.
Related patents, include, for example, the U.S. Pat. No. 5,703,407 entitled xe2x80x9cRESIN-SEALED TYPE SEMICONDUCTOR DEVICExe2x80x9d; and the U.S. Pat. No. 5,519,251 entitled xe2x80x9cSEMICONDOCTOR DEVICE AND METHOD OF PRODUCING THE SAMExe2x80x9d; to name just a few.
The U.S. Pat. No. 5,703,407 discloses an LOC (Lead-On-Chip) type of QFN technology. One drawback to this patented technology, however, is that it provides no exposed die pad on the bottom side of the encapsulation body, so that it would be undesirably poor in grounding effect and heat-dissipation efficiency.
The U.S. Pat. No. 5,519,251 discloses a so-called SON (Small Outline Non-leaded) packaging technology, which is characterized by the use of two leadframes to provide support for the packaged chip and help enhance the heat-dissipation efficiency. One drawback to this patented technology, however, is that it provides no direct coupling between the die pad and PCB""s ground plane, resulting in a poor grounding effect to the packaged chip.
It is therefore an objective of this invention to provide a new QFN semiconductor packaging technology that can be used to package a semiconductor chip of central-pad type.
It is another objective of this invention to provide a new QFN semiconductor packaging technology that allows the packaged chip, particularly high-frequency and radio-frequency chip, to have enhanced grounding effect and electrical performance during operation.
In accordance with the foregoing and other objectives, the invention proposes a new QFN semiconductor packaging technology.
The QFN package structure according to the invention comprises: (a) a leadframe including a plurality of leads, a chip-support-and-grounding structure, and at least one ground wing; wherein the chip-support-and-grounding structure serves both as a die pad and a ground bus, and the ground wing is electrically linked to the chip-support-and-grounding structure; (b) at least one semiconductor chip of central-pad type having an active surface and an inactive surface and having at least one row of bond pads arranged along a center line on the active surface thereof; the semiconductor chip being attached to the leadframe in such a manner that its active surface is adhered to the chip-support-and-grounding structure and its bond pads are aligned to the chip-support-and-grounding structure; (c) a set of bonding wires for electrically coupling the semiconductor chip to the leads; and (d) an encapsulation body for encapsulating the semiconductor chip and the leadframe, while exposing the ground wing as well as the outer portions of the leads to the outside of the encapsulation body.
The QFN packaging process according to the invention comprising the step of: (1) preparing a leadframe including a plurality of leads, a chip-support-and-grounding structure, and at least one ground wing; wherein the chip-support-and-grounding structure serves both as a die pad and a ground bus, and the ground wing is electrically linked to the chip-support-and-grounding structure; (2) attaching the semiconductor chip to the lead-frame in such a manner that the active surface of the semiconductor chip is adhered to the ground bus, and the bond pads thereof are aligned to the chip-support-and-grounding structure; (3) performing a wire-bonding process to bond a set of bonding wires for electrically coupling the semiconductor chip to the leads; and (4) performing an encapsulation process to form an encapsulation body for encapsulating the semiconductor chip and the leadframe, while exposing the ground wing as well as the outer portions of the leads to the outside of the encapsulation body.
The QFN semiconductor packaging technology according to the invention is characterized by that it includes a ground-wing structure which is exposed to the bottom outside of the encapsulation body. This feature can help enhance the grounding effect and the electrical performance of the packaged chip during operation.